// 
// Author: Hans Summers, 2015
// Website: http://www.hanssummers.com
//
// A very very simple Si5351a demonstration
// using the Si5351a module kit http://www.hanssummers.com/synth
// Please also refer to SiLabs AN619 which describes all the registers to use
//
#include <xc.h>         //Provides PIC header file and is required for CCI compliance
#include "si5351a.h"

// 
// Set CLK0 output ON and to the specified frequency
// Frequency is in the range 1MHz to 150MHz
// Example: si5351aSetFrequency(10000000);
// will set output CLK0 to 10MHz
//
// This example sets up PLL A
// and MultiSynth 0
// and produces the output on CLK0
//
void si5351aSetFrequency(unsigned long frequency)
{
	unsigned long pllFreq;
	unsigned long xtalFreq = Si5351A_XTAL_FREQ;
	unsigned long l;
	float f;
	unsigned char mult;
	unsigned long num;
	unsigned long denom;
	unsigned long divider;

	divider = 900000000 / frequency;// Calculate the division ratio. 900,000,000 is the maximum internal 
									// PLL frequency: 900MHz
	if (divider % 2) divider--;		// Ensure an even integer division ratio

	pllFreq = divider * frequency;	// Calculate the pllFrequency: the divider * desired output frequency

	mult = pllFreq / xtalFreq;		// Determine the multiplier to get to the required pllFrequency
	l = pllFreq % xtalFreq;			// It has three parts:
	f = l;							// mult is an integer that must be in the range 15..90
	f *= 1048575;					// num and denom are the fractional parts, the numerator and denominator
	f /= xtalFreq;					// each is 20 bits (range 0..1048575)
	num = f;						// the actual multiplier is  mult + num / denom
	denom = 1048575;				// For simplicity we set the denominator to the maximum 1048575

									// Set up PLL A with the calculated multiplication ratio
	setupPLL(SI_SYNTH_PLL_A, mult, num, denom);
									// Set up MultiSynth divider 0, with the calculated divider. 
									// The final R division stage can divide by a power of two, from 1..128. 
									// represented by constants SI_R_DIV1 to SI_R_DIV128 (see si5351a.h header file)
									// If you want to output frequencies below 1MHz, you have to use the 
									// final R division stage
	setupMultisynth(SI_SYNTH_MS_0, divider, SI_R_DIV_1);
									// Reset the PLL. This causes a glitch in the output. For small changes to 
									// the parameters, you don't need to reset the PLL, and there is no glitch
	sendRegister(SI_PLL_RESET, 0xA0);	
									// Finally switch on the CLK0 output (0x4F)
									// and set the MultiSynth0 input to be PLL A
	sendRegister(SI_CLK0_CONTROL, 0x4F | SI_CLK_SRC_PLL_A);
}


// Set up specified PLL with mult, num and denom
// mult is 15..90
// num is 0..1,048,575 (0xFFFFF)
// denom is 0..1,048,575 (0xFFFFF)
//
void setupPLL(unsigned char pll, unsigned char mult, unsigned long num, unsigned long denom)
{
	unsigned long P1;					// PLL config register P1
	unsigned long P2;					// PLL config register P2
	unsigned long P3;					// PLL config register P3

	P1 = (unsigned long)(128 * ((float)num / (float)denom));
	P1 = (unsigned long)(128 * (unsigned long)(mult) + P1 - 512);
	P2 = (unsigned long)(128 * ((float)num / (float)denom));
	P2 = (unsigned long)(128 * num - denom * P2);
	P3 = denom;

	sendRegister(pll + 0, (P3 & 0x0000FF00) >> 8);
	sendRegister(pll + 1, (P3 & 0x000000FF));
	sendRegister(pll + 2, (P1 & 0x00030000) >> 16);
	sendRegister(pll + 3, (P1 & 0x0000FF00) >> 8);
	sendRegister(pll + 4, (P1 & 0x000000FF));
	sendRegister(pll + 5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16));
	sendRegister(pll + 6, (P2 & 0x0000FF00) >> 8);
	sendRegister(pll + 7, (P2 & 0x000000FF));
}

//
// Set up MultiSynth with integer divider and R divider
// R divider is the bit value which is OR'ed onto the appropriate register, it is a #define in si5351a.h
//
void setupMultisynth(unsigned char synth, unsigned long divider, unsigned char rDiv)
{
	unsigned long P1;					// Synth config register P1
	unsigned long P2;					// Synth config register P2
	unsigned long P3;					// Synth config register P3

	P1 = 128 * divider - 512;
	P2 = 0;							// P2 = 0, P3 = 1 forces an integer value for the divider
	P3 = 1;

	sendRegister(synth + 0,   (P3 & 0x0000FF00) >> 8);
	sendRegister(synth + 1,   (P3 & 0x000000FF));
	sendRegister(synth + 2,   ((P1 & 0x00030000) >> 16) | rDiv);
	sendRegister(synth + 3,   (P1 & 0x0000FF00) >> 8);
	sendRegister(synth + 4,   (P1 & 0x000000FF));
	sendRegister(synth + 5,   ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16));
	sendRegister(synth + 6,   (P2 & 0x0000FF00) >> 8);
	sendRegister(synth + 7,   (P2 & 0x000000FF));
}

//
// Switches off Si5351a output
// Example: si5351aOutputOff(SI_CLK0_CONTROL);
// will switch off output CLK0
//
void si5351aOutputOff(unsigned char clk)
{
	sendRegister(clk, 0x80);		// Refer to SiLabs AN619 to see bit values - 0x80 turns off the output stage
}


//****************************************
/*This function follows the description in Silabs Si5251a data sheet section 4
in particular, figure 9 for i2c write operation.  NB 'Burst Mode' writing cannot be
used as the required register addresses are not contiguous*/
void sendRegister (unsigned char reg, unsigned char data)
{
    StartI2C ();
	masterSendI2C (SI5351A_ADDRESS | 0x00);  //Sends si5351a address and 'write' bit
	masterSendI2C (reg);
    masterSendI2C (data);
    StopI2C ();
}

//****************************************